Samsung Electronics Says It Sells Bandwidth, Not Bits, in the AI Era — zHBM Slated for 2029 Debut — BigGo Finance

Samsung Electronics has positioned memory bandwidth as the core competitive advantage of the artificial intelligence (AI) era, projecting that its next-generation high-bandwidth memory (HBM) product, zHBM, will arrive sooner than the market had anticipated.

Cho Sang-yeon, executive vice president and head of Samsung Electronics’ Device Solutions America (DSA), made the remarks on the 27th (local time) as a speaker at The Six Five Summit 2026, a U.S. information technology (IT) conference held online. In a 30-minute discussion titled “Redefining AI’s Limits: Samsung’s Memory, Power, and System Design,” he assessed that the AI infrastructure paradigm is fundamentally shifting from compute-centric to memory-centric.

Cho pointed out that “the industry still doesn’t properly understand that the ‘tokens per second an organization needs’ — a critical factor in AI inference services — is determined by memory bandwidth.” Memory bandwidth, which measures how quickly data can move between memory and compute units, dictates user capacity, request volume, response speed, and context preservation and throughput, he explained. Not only the level of service an AI system can deliver, but also the cost required to implement it, hinges on memory bandwidth.

“Samsung is not selling ‘bits’ — it is selling ‘bandwidth,'” Cho said. “The applications that succeed four years from now won’t be the ones with the most memory, but the ones that figure out how to utilize the memory bandwidth they have.”

Accordingly, he proposed “memory-centric computing” as an alternative approach: starting with memory as the point of departure, establishing the required bandwidth, and then finding ways to utilize it efficiently. Under the conventional approach, compute resources were decided first, followed by memory capacity, with packaging and power considerations reviewed afterward. Going forward, he argued, that sequence should be inverted so that memory is considered first.

As a product designed to boost memory bandwidth, Cho cited zHBM, which Samsung Electronics recently unveiled. Unlike the conventional approach of connecting HBM alongside the AI accelerator (xPU) that handles computation, zHBM stacks HBM directly on top of the accelerator, minimizing data travel distance and maximizing bandwidth.

“We are currently defining first-generation zHBM specifications, and future products based on this are expected to emerge after 2029,” Cho said. That timeline is roughly one year earlier than market forecasts, which had pointed to commercialization around 2030. He did, however, flag thermal issues as a key challenge to be resolved during development, adding that Samsung is applying technologies including hybrid copper bonding (HCB) to address them.

Cho also identified advanced packaging as another area of growing importance alongside memory bandwidth. As process-node shrinks alone reach their limits in delivering the performance and power efficiency AI demands, packaging technology — which combines multiple dies, memory, and different process nodes into a single system — is playing an increasingly critical role.

“Some companies outsource the base die externally and manage handoffs between processes,” Cho said. “Samsung, by contrast, directly manages the integration process to achieve design goals at every level — system, chip, and memory.” With HBM4, for example, Samsung designs the base die in-house using its advanced 4-nanometer process and manages assembly and packaging end-to-end, enabling optimization of system-wide objectives including power efficiency, signal integrity, performance, and bandwidth.

Cho also said Samsung plans to bring its second semiconductor fabrication facility in Taylor, Texas — Taylor Fab 2 — online within a few years to expand production capacity for advanced process nodes, including 2-nanometer (nm), and support U.S. customers.