TSMC’s CoWoS Hits Yield and Cost Bottlenecks; Analysts Say Intel’s EMIB Is Poised to Gain Ground — BigGo Finance

The advanced packaging battlefield for AI chips is undergoing a subtle shift. Taiwan Semiconductor Manufacturing (2330.TW) has long dominated the integrated packaging of AI accelerators and High Bandwidth Memory (HBM) with its CoWoS technology, but market research firms have recently pointed out that this solution is confronting structural bottlenecks including rising costs, yield risks, and capacity constraints—opening a window of opportunity for Intel’s EMIB technology, which the company has been developing for years.

According to a report by EE Times, Neil Shah, co-founder of research firm Counterpoint Research, analyzed that TSMC’s CoWoS has served major AI chip players such as Nvidia, AMD, and Broadcom for years. However, HBM’s heavy reliance on silicon interposer architecture brings high costs, including increased package thickness, yield risks, capacity limitations, and substantial scrap costs.

Shah identified the most problematic stage of the CoWoS architecture as the final packaging step. He noted that large dies inherently have higher defect rates. If the interposer fails during the final process step, the GPU die and the more than eight HBM stacks connected to it are all scrapped together—meaning the loss of an entire chip worth thousands of dollars at the very last stage.

By contrast, Intel’s EMIB (Embedded Multi-die Interconnect Bridge) takes a different technical path. EMIB embeds localized silicon bridges within an organic substrate, enabling high-speed die-to-die interconnects without requiring a large-area silicon interposer. The technology has already been deployed in volume production for Intel’s Sapphire Rapids and Ponte Vecchio products. Shah believes that Intel’s EMIB, along with its future ZAM and XBM technologies, can help AI chip designers avoid the problems inherent in the CoWoS architecture.

The CEO of International Business Strategies also noted that Intel’s packaging already has a number of significant external customers, with considerable growth potential over the next few years. He described Intel’s packaging technology as excellent, and the company is currently expanding capacity in New Mexico.

Supply chain investigations reveal that Google’s next-generation TPU, developed in partnership with MediaTek (2454.TW), will adopt Intel’s EMIB-T technology. Shah emphasized that if Google indeed shifts to Intel, the impact would be enormous, given that Google is already the world’s second-largest AI accelerator company. Nvidia and AMD currently show no clear signs of diversifying their suppliers.

However, Intel still faces considerable obstacles in truly shaking TSMC’s position. Shah stated that, for now, TSMC’s CoWoS paired with HBM remains the safest and most flexible universal platform, capable of simultaneously meeting both AI training and inference requirements.

Analyst Mike Demler also holds a cautious view. He believes TSMC’s existing CoWoS process yields remain excellent. While the newer CoWoS-L variant may have faced initial yield issues, there is currently no evidence of a systemic yield crisis; the real confirmed pressure remains capacity shortages. Even so, as long as AI customers begin seeking second sources, Intel has the opportunity to leverage EMIB, Foveros, and subsequent ZAM and XBM technologies to turn advanced packaging into a new trump card for re-entering the AI battlefield.

Intel recently unveiled three AI architectures at Hot Chips 2026. Its next-generation Xeon processor, Diamond Rapids, targets enterprise-grade agentic AI with up to 256 cores and 16 memory channels; Crescent Island targets low-power AI inference; and Wildcat Lake extends AI capabilities to client and edge devices. Compared with its past singular focus on more powerful processors, Intel’s greater leverage now may come from its manufacturing and advanced packaging capabilities.

Notably, the packaging battle is not merely a two-horse race between TSMC and Intel. Major OSAT provider Powertech Technology (6239.TW) recently announced its proprietary PiFO panel-level packaging technology, with mass production of its FOPLP line integrating major customers’ ASICs and HBM chips expected by mid-2027. Powertech’s PiFO is conceptually similar to CoWoS-L but uses a square panel layout; a 510×515 panel can yield 45 to 90 units, delivering greater output efficiency. The biggest difference from Intel’s EMIB is that PiFO’s oS segment uses standard ABF substrates rather than EMIB’s cavity-embedded substrate approach, resulting in higher yields.

Industry analysis indicates that Powertech’s panel-level packaging line involves capital investment exceeding NT$20 billion (approximately $630.3 million). It is currently operating at a loss, eroding earnings per share by about NT$3 annually. Once it reaches mass production scale economies by mid-next year, it is expected to contribute at least NT$3 per share in annual net profit to Powertech.

The competitive landscape for advanced packaging is evolving from TSMC’s singular dominance toward a diversified supply base. For AI chip designers, the emergence of second sources means enhanced bargaining power and supply chain risk diversification. For Intel, this could be the critical breakthrough for reclaiming leadership in wafer manufacturing and packaging. For TSMC, the key challenge over the coming year will be maintaining its CoWoS leadership while addressing customer concerns about cost and capacity.